1. Field of the Invention
The present invention relates to a method for testing a semiconductor memory device, and more particularly to a method for testing a semiconductor memory device by use of a test circuit having, for example, the semiconductor memory device to be tested and logic circuits mounted thereon.
2. Description of the Related Art
FIG. 10 is a circuit diagram showing the configuration of a test circuit employed by a conventional method for testing a semiconductor memory device.
In the figure, reference numeral 5 denotes a test circuit for testing a DRAM 52 having a capacity of 16 Mbits, and the test circuit 5 is connected to a testing device (hereinafter referred to as a tester) not shown. Reference numeral 51 denotes an 8-bit D flip-flop which receives 8-bit input data TDI output from the tester through its input D (7:0) and holds the data upon a rise of a write clock signal TWCK. The output Q (7:0) of the 8-bit D flip-fop 51 is controlled according to an output control signal TOE-.
Reference numeral 52 indicates a 16 Mbit DRAM (Dynamic Random Access Memory) used as a semiconductor memory device sample to be tested, and has a wide data bus of, for, example, an (mxc3x97n)-bit widthxe2x80x94in the example of FIG. 10, m=8 (bits) and n=16 (stages), totaling 128 bits. There are 4096 row addresses and 32 column addresses, that is, a 12-bit row address line and a 5-bit column address line, respectively, totaling 17 bits for the row and column address lines.
Reference numeral 53 denotes a 128-to-8 multiplexer which reads (8xc3x9716)-bit data from the 16 Mbit DRAM 52, selects a set of an 8-bit data from the read (8xc3x9716)-bit data based on an output data selection signal TSEL fed from the tester, and outputs the selected 8-bit data as an 8-bit output data TDO.
The number 4, 8, or 17 given to each line indicates the number of data bits employed for the line, and the bracketed numbers  less than 0 greater than  to  less than 15 greater than  each indicate corresponding an 8-bit data.
The operation of the test circuit will be explained below.
Description will be first made of write operation to the 16 Mbit DRAM 52.
The input data TDI output from the tester is input to the input D (7:0) of the D flip-flop 51, and held upon a rise of a write clock signal TWCK. At that time, when the tester outputs an output control signal TOE- having a high level (H level signal) so as to apply the H level signal to the OE terminal of the D flip-flop 51, an 8-bit data is output from the output Q (7:0) of the D flip-flop 51.
The data output from the output Q (7:0) of the D flip-flop 51 branches out into 16 sets of data each having 8 bits. Then, the tester enters an address signal TADI, which indicates a row address and a column address, and an address strobe signal TAS- having a low level (an L level), to the corresponding terminals of the 16 Mbit DRAM 52. The current address signal TADI is introduced into the 16 Mbit DRAM 52 at a timing according to the address strobe signal TAS-. With the timing of introduction of the address signal TADI into the 16 Mbit DRAM 52, the tester outputs a write control signal TW- having an L level, and as result, the data which has branched out into the 16 sets of data each having 8 bits is written into a memory area in the 16 Mbit DRAM 52 specified by the address signal TADI through a terminal D (127:0). At that time, since an output control signal TOE- having an H level is fed to the 16 Mbit DRAM 52, the output of the 16 Mbit DRAM 52 is disabled.
Next, description will be made of read operation from the 16 Mbit DRAM 52.
The tester enters an address signal TADI, which indicates a row address and a column address, and an address strobe signal TAS- having an L level, to the corresponding terminals of the 16 Mbit DRAM 52. The current address signal TADI is introduced into the 16 Mbit DRAM 52 at a timing according to the address strobe signal TAS-. With the timing of introduction of the address signal TADI into the 16 Mbit DRAM 52, the tester outputs an output control signal TOE- having an L level, and as result, (8xc3x9716)-bit data which has been written into a memory area in the 16 Mbit DRAM 52 specified by the introduced address signal TADI is read out at the same time. At that time, since the tester outputs a write control signal TW- having an H level and an output control signal TOE- having an L level, both write operation to the 16 Mbit DRAM 52 and output from the output Q (7:0) of the D flip-flop 51 are disabled.
The multiplexer 53 selects a set of 8-bit data from (8xc3x9716)-bit data delivered from the output Q (127:0) of the 16 Mbit DRAM 52 based on an output data selection signal TSEL entered from the tester, and outputs the selected set of 8-bit data as an output data TDO.
Description will be made of the procedure of a conventional method for testing a semiconductor memory device using the above test circuit.
FIG. 11 is a flowchart showing the procedure of a conventional method for testing a semiconductor memory device. It is assumed that the 16 Mbit DRAM 52 having a wide data bus of an (mxc3x97n)-bit width has a row address size of x and a column address size of y.
To begin with, (mxc3x97n)-bit data entered from the tester is fed to the input D (7:0) of the D flip-flop 51 in units of m bits sequentially as input data TDI, and delivered from the output Q (7:0) when the output control signal TOE- is at an H level. Then, the tester sets the row address X and the column address Y so that X=0 and Y=0, at step ST100.
To write the data into the 16 Mbit DRAM 52, the tester enters an address signal TADI indicating that the row address X=0 and the column address Y=0, and an address strobe signal TAS- having an L level to the corresponding terminals of the 16 Mbit DRAM 52. The current address signal TADI is introduced into the 16 Mbit DRAM 52 at a timing according to the address strobe signal TAS-. With the timing of introduction of the address signal TADI into the DRAM 52, the tester outputs a write control signal TW- having an L level, and as a result, the (mxc3x97n)-bit data is written into a memory area (X=0, Y=0) in the 16 Mbit DRAM 52 specified by the address signal TADI at step ST101.
To read out the data written into the 16 Mbit DRAM 52, the tester enters an address signal TADI indicating that the row address X=0 and the column address Y=0, and an address strobe signal TAS- having an L level to the corresponding terminals of the 16 Mbit DRAM 52. The current address signal TADI is introduced into the 16 Mbit DRAM 52 at a timing according to the address strobe signal TAS-. With the timing of introduction of the address signal TADI into the DRAM 52, the tester outputs an output control signal TOE- having an L level, and as a result, the (8xc3x9716)-bit data which has been written into the memory area (X=0, Y=0) in the 16 Mbit DRAM 52 specified by the introduced address signal TADI is read out at the same time at step ST102. The multiplexer 53 selects m-bit data indicated by a number N of 0 from the read-out n sets of m-bit data according to an output data selection signal TSEL delivered from the tester, and outputs the selected m-bit data as output data TDO at step ST103. The tester receives the output data TDO, and compares it with an expected value of the corresponding m-bit data to determine whether the output data TDO is correct at step ST104.
If it is determined that the output data TDO is erroneous, the tester obtains the corresponding defective bit information (indicating that the row address X=0, the column address Y=0, and the number N given to the compared m-bit data=0) at step ST105. Then, to test the next m-bit output data TDO, the tester adds 1 to the number N given to the current m-bit data at step ST106, and determines whether the number N is equal to or larger than n at step ST107. On the other hand, at step ST104, if it is determined that the output data TDO is correct, the tester also adds 1 to the number N given to the current m-bit data in order to test the next m-bit output data TDO at step ST106, and determines whether the number N is equal to or larger than n at step ST107.
If the number N is smaller than n, the multiplexer 53 selects m-bit data corresponding to the updated number N according to an output data selection signal TSEL delivered from the tester, and outputs the selected m-bit data as output data TDO at step ST108. The tester then compares the output data TDO with an expected value of the corresponding m-bit data to determine whether the output data TDO is correct. This procedure (steps ST104 through ST108) is repeated.
If it is determined that the number N is equal to or larger than n at step ST107, on the other hand, the tester adds 1 to the column address Y at step ST109, and determines whether the updated column address Y is larger than the column address size y at step ST110. If the column address Y is equal to or smaller than the column address size y, the tester introduces an address signal TADI indicating the updated column address Y by use of an address strobe signal TAS- having an L level, writes and then reads out (mxc3x97n)-bit data from the updated column address Y, and determines whether each m-bit data selected by the multiplexer 53 is correct at steps ST101 through ST110.
If it is determined that the updated column address Y is larger than the column address size y at step ST110, on the other hand, the tester adds 1 to the row address X and sets the column address Y to 0 at step ST111., and determines whether the row address X is larger than the row address size x at step ST112. If the row address X is equal to or smaller than the row address size x, the tester introduces an address signal TADI indicating the updated row address X and column address Y by use of an address strobe signal TAS- having an L level, writes and then reads out (mxc3x97n)-bit data, and determines whether each m-bit data selected by the multiplexer 53 is correct at steps ST101 through ST112 as described above. This procedure is repeated. If it is determined that the updated row address X is larger than the row address size x at step ST112, on the other hand, the testing of this 16 Mbit DRAM 52 is ended.
With the recent progress in techniques for producing more miniaturized and more highly integrated semiconductor integrated circuits, components such as DRAMs have acquired a greater capacity and a larger number of bits, lately at a rapid pace, which has required shortening of man hours for testing these DRAMs. In the conventional method for testing a semiconductor memory device, however, to test (mxc3x97n)-bit data for each address, the data is tested in units of m bits n times, and this test is repeated for each row address and each column address, that is, the test is repeated a number of times equal to the row address size multiplied by the column address size. Accordingly, it is necessary to repeat the test xxc3x97yxc3x97n times to check all bits of the semiconductor memory device, requiring a large number of man hours and high cost.
The present invention is provided for solving the problems aforementioned, and it is an object of the present invention to provide a test method for a semiconductor memory device capable of reducing the number of man hours required for the test by determining whether (mxc3x97n)-bit data is correct at the same time when the (mxc3x97n)-bit data is read out, and ending the test if data in all addresses of the semiconductor memory device is correct, or testing the data in units of m bits otherwise.
According to one aspect of the present invention, a method for testing a semiconductor memory device tests a semiconductor memory device having a wide data bus of an (mxc3x97n)-bit width and includes a first process and a second process, wherein the first process comprises the steps of: reading out (mxc3x97n)-bit data written into each address of the semiconductor memory device; comparing the read-out (mxc3x97n)-bit data with the corresponding (mxc3x97n)-bit data of its before-written state to determine whether the read-out (mxc3x97n)-bit data is correct; obtaining, if it is determined that the read-out (mxc3x97n)-bit data is erroneous, an address corresponding to the erroneous data as a defective address; and ending testing of the semiconductor memory device if it is determined that the read-out (mxc3x97n)-bit data from all addresses of the semiconductor memory device is correct; whereas the second process comprises the steps of: writing (mxc3x97n)-bit data into the obtained defective address and then reading out the written (mxc3x97n)-bit data; and comparing each m-bit data constituting the read-out (mxc3x97n)-bit data with an expected value of a predetermined m-bit data to determine whether the each m-bit data constituting the read-out (mxc3x97n)-bit data is correct.
According to another aspect of the present invention, a method for testing a semiconductor memory device tests a semiconductor memory device having a wide data bus of an (mxc3x97n)-bit width and includes a first process and a second process, wherein the first process comprising the steps of: reading out (mxc3x97n)-bit data written into each address of the semiconductor memory device; comparing the read-out (mxc3x97n)-bit data with the corresponding (mxc3x97n)-bit data of its before-written state to determine whether the read-out (mxc3x97n)-bit data is correct; obtaining, if it is determined that the read-out (mxc3x97n)-bit data is erroneous, an address corresponding to the erroneous data as a defective address; and ending testing of the semiconductor memory device if it is determined that the read-out (mxc3x97n)-bit data from all addresses of the semiconductor memory device is correct; whereas the second process comprises the steps of: writing (mxc3x97n)-bit data into the obtained defective address and then reading out the written (mxc3x97n)-bit data; dividing the read-out (mxc3x97n)-bit data into pieces each having a number of bits smaller than mxc3x97n and larger than m; comparing each piece of the divided read-out data having said number of bits with a corresponding piece of data obtained as a result of dividing the (mxc3x97n)-bit data of its before-written state into pieces each having said number of bits to determine whether the each piece of the divided read-out data is correct; and comparing each m-bit data constituting an erroneous piece of the divided read-out data having said number of bits with an expected value of a predetermined m-bit data to determine whether the each m-bit data constituting the erroneous piece of the divided read-out data is correct.
According to still another aspect of the present invention, in the above method for testing a semiconductor memory device, wherein the first process specifies each address of the semiconductor memory device by increasing or decreasing a row address of the semiconductor memory device by one address at a time for each row, or by increasing or decreasing a column address of the semiconductor memory device by one address at a time for each column in order to test the semiconductor memory device.
According to yet another aspect of the present invention, the above method for testing a semiconductor memory device further includes a third process employed before the first process, the third process comprising the steps of: specifying each address of the semiconductor memory device by increasing or decreasing both a row address and a column address of the semiconductor memory device simultaneously by one address at a time; reading out (mxc3x97n)-bit data written into each address of the semiconductor memory device; comparing the read-out (mxc3x97n)-bit data with the corresponding (mxc3x97n)-bit data of its before-written state to determine whether the read-out (mxc3x97n)-bit data is correct; obtaining, if it is determined that the read-out (mxc3x97n)-bit data is erroneous, an address corresponding to the erroneous data as a defective address and determining whether defective memory cells corresponding to the defective address can be repaired by replacing the defective memory cells with redundant memory cells held by the semiconductor memory device; and ending testing of said semiconductor memory device if it is determined that the defective memory cells cannot be repaired.
According to still a further aspect of the present invention, in the above method for testing a semiconductor memory device, wherein the first process further comprises a step of: determining whether defective memory cells corresponding to the defective address can be repaired by replacing the defective memory cells with redundant memory cells held by the semiconductor memory device, if it is determined that (mxc3x97n)-bit data stored in a predetermined address is erroneous.
According to yet another aspect of the present invention, in the above method for testing a semiconductor memory device, the second process further comprises a step of: determining whether defective memory cells corresponding to the erroneous m-bit data can be repaired by replacing the defective memory cells with redundant memory cells held by the semiconductor memory device, if it is determined from comparison of m-bit data with an expected value of predetermined m-bit data that the former m-bit data is erroneous.
According to still another aspect of the present invention, in the above method for testing a semiconductor memory device, in the case where one of the first process, the second process, and the third process determines whether a semiconductor memory device which has some defective memory cells corresponding to a defective address or erroneous m-bit data can be repaired by replacing the defective memory cells with redundant memory cells held by the semiconductor memory device, if the number of the defective memory cells is smaller than the number of the redundant memory cells, it is determined that the defective semiconductor memory device can be repaired.